Field of the Invention
The present invention relates to a thin film transistor array substrate to be used in a liquid crystal display device, and a method for manufacturing the substrate.
Description of the Background Art
Conventionally, liquid crystal display devices have a structure where a TFT array substrate (hereinafter, “array substrate”) formed with a pixel electrode and a thin film transistor (TFT) for supplying a display signal to the pixel electrode, a counter substrate formed with a common electrode, and a liquid crystal layer held therebetween. The liquid crystal display devices that employ a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode are the mainstream. In the TN mode, liquid crystal is driven by an electric field in a vertical direction (the direction vertical to the surface of the array substrate and the counter electrode) generated between the pixel electrode and the common electrode. In recent years, liquid crystal display devices that employ an IPS (In-Plane Switching) mode (“IPS” is registered trade mark), and an FFS (Fringe Field Switching) mode are put to practical use. In these modes, both a pixel electrode and a common electrode are disposed on an array substrate, and an electric field in a lateral direction generated between the pixel electrode and the common electrode drives liquid crystal.
For example, Japanese Patent Application Laid-Open No. 2009-128397 (Patent Document 1) proposes a structure where a thick insulating film (planarizing film) is formed on a source wiring (display signal line), and an upper portion of the source wiring is coated with a common electrode in a liquid crystal display panel of the FFS mode. With this structure, the common electrode on the source wiring shields an electric field from a pixel and simultaneously a parasitic capacitance between the pixel and the source wiring is repressed so that power consumption of the liquid crystal display panel can be reduced.
In a liquid crystal display panel of FFS mode, a pixel electrode and a common electrode are formed on different layers. For this reason, at least two dry etching steps are necessary for forming a first aperture (contact hole) that connects the common electrode and a wiring (common wiring) for supplying an electric potential to the common electrode, and a second aperture that connects the pixel electrode and a drain electrode of TFT for supplying a display signal to the pixel electrode.
Further, prior to the step of forming the second aperture, when the planarizing film on the drain electrode of TFT is removed in the step of forming the first aperture, the surface of the drain electrode is damaged twice by dry etching for forming the first aperture and dry etching for forming the second aperture. This occasionally causes an increase in contact resistance between the pixel electrode and the drain electrode. On the other hand, when the first aperture and the second aperture are simultaneously formed, one more aperture should be formed to connect the common electrode with the common wiring, and thus an area ratio of contact holes within a pixel region increases.
Further, when a planarizing film (organic planarizing film) whose material is organic resin is used, the organic planarizing film remains in a region other than the apertures at terminal portions. For this reason, a new countermeasure against weakening of an adhesion at packaging time is necessary.